//--------------------------------------------------------------------------------------------
//    : 
//      Component name  : fpmul_stage2
//      Author          : 
//      Company         : 
//
//      Description     : 
//
//
//--------------------------------------------------------------------------------------------


module FPmul_stage2(A_EXP, A_SIG, B_EXP, B_SIG, SIGN_out_stage1, clk, isINF_stage1, isNaN_stage1, isZ_tab_stage1, EXP_in, EXP_neg_stage2, EXP_pos_stage2, SIGN_out_stage2, SIG_in, isINF_stage2, isNaN_stage2, isZ_tab_stage2);
   input [7:0]   A_EXP;
   input [31:0]  A_SIG;
   input [7:0]   B_EXP;
   input [31:0]  B_SIG;
   input         SIGN_out_stage1;
   input         clk;
   input         isINF_stage1;
   input         isNaN_stage1;
   input         isZ_tab_stage1;
   output [7:0]  EXP_in;
   reg [7:0]     EXP_in;
   output        EXP_neg_stage2;
   reg           EXP_neg_stage2;
   output        EXP_pos_stage2;
   reg           EXP_pos_stage2;
   output        SIGN_out_stage2;
   reg           SIGN_out_stage2;
   output [27:0] SIG_in;
   reg [27:0]    SIG_in;
   output        isINF_stage2;
   reg           isINF_stage2;
   output        isNaN_stage2;
   reg           isNaN_stage2;
   output        isZ_tab_stage2;
   reg           isZ_tab_stage2;
   
   
   wire [7:0]    EXP_in_int;
   wire          EXP_neg_int;
   wire          EXP_pos_int;
   wire [27:0]   SIG_in_int;
   wire          dout;
   reg [7:0]     dout1;
   reg [63:0]    prod;
   
   assign SIG_in_int = prod[47:20];
   
   assign EXP_in_int = {((~dout1[7])), dout1[6:0]};
   
   
   always @(posedge clk)
      
      begin
         EXP_in <= EXP_in_int;
         SIG_in <= SIG_in_int;
         EXP_pos_stage2 <= EXP_pos_int;
         EXP_neg_stage2 <= EXP_neg_int;
      end
   
   
   always @(posedge clk)
      
      begin
         isINF_stage2 <= isINF_stage1;
         isNaN_stage2 <= isNaN_stage1;
         isZ_tab_stage2 <= isZ_tab_stage1;
         SIGN_out_stage2 <= SIGN_out_stage1;
      end
   
   assign EXP_pos_int = A_EXP[7] & B_EXP[7];
   assign EXP_neg_int = (((A_EXP[7] == 1'b0 & (~(A_EXP == 8'h7F))) & (B_EXP[7] == 1'b0 & (~(B_EXP == 8'h7F))))) ? 1'b1 : 
                        1'b0;
   
   reg [8:0]     mw_I4t0;
      reg [8:0]     mw_I4t1;
      reg [8:0]     mw_I4sum;
      reg           mw_I4carry;

   always @(A_EXP or B_EXP or dout)
   begin: I4combo
      mw_I4t0 = {1'b0, A_EXP};
      mw_I4t1 = {1'b0, B_EXP};
      mw_I4carry = dout;
      mw_I4sum = mw_I4t0 + mw_I4t1 + mw_I4carry;
      dout1 <= (mw_I4sum[7:0]);
   end
   
      reg [63:0]     dtemp;   
   always @(A_SIG or B_SIG)
   begin: I2combo
      dtemp = (A_SIG * B_SIG);
      prod <= dtemp;
   end
   
   assign dout = 1'b1;
   
endmodule
